Thursday, April 24, 2014: Anritsu Corporation is launching sales of its new Clock Recovery options for MP1800A Signal Quality Analyzer (SQA) as R&D BER testing solution for high-speed interconnects up to 32.1 Gbit/s.
The MP1800A SQA is a modular-type BERT composed of a Pulse Pattern Generator (PPG), plus a high-input sensitivity Error Detector (ED). A Jitter modulation source can also be installed in the SQA to generate various types of jitter, including SJ, RJ, BUJ, SSC, etc., for device jitter tolerance tests. Adding today’s newly announced clock recovery options supports BER measurements and jitter tolerance tests for SERDES, Active Optical Cables (AOC), optical transceiver modules, etc., using just the all-in-one MP1800A SQA.
The continuing explosive expansion in data traffic is driving demand for even faster digital communications systems. To increase processing speeds, high-performance servers in data centers are standardizing on high-speed serial communications methods exceeding 25 Gbit/s, such as 100GbE (100G Base CR4, KR4), InfiniBand EDR, CEI-28G, 32G FC, etc., and trunk communications networks are developing next-generation transmission technologies with speeds of 400 Gbit/s.
The SERDES devices, AOC, and optical transceiver modules needed to achieve these high-speed serial communications send and receive serial data without transmitting synchronous clock signals. Previously, BER and Jitter Tolerance measurements of these systems require external clock recovery instrument. Newly announced internal clock recovery options enable one box testing without external instrument.
Anritsu developed its MP1800A Signal Quality Analyzer as a platform for evaluating high-speed interconnects. It already supports BERT and jitter measurements up to 32 Gbit/s and installing the new clock recovery options announced today strengthens its functions further clock-less device BER measurements and jitter tolerance measurements for more accurate and ideal signal integrity analyses for various applications.
